Recent improvements in Complementary Metal Oxide Semiconductor (CMOS) technology have resulted in extremely narrow channel transistor devices having lengths of 0.5 .mu.m and less. One advantage of these narrow devices is their ability to be densely packed on integrated circuits. As circuit designers have exploited this density feature, integrated circuit power consumption has increasingly become an important design issue. One technique for lowering system power consumption has been to reduce integrated circuit power supply voltages from a typical 5 Volts (V), to voltages in the range of from about 1.8 to about 3.3 V. A CMOS integrated circuit designed for use in low voltage systems requires thin gate-oxide transistors in order to maintain high overall device performance.
The problem created by thin gate oxide devices is that they are difficult to use in combination with higher voltage devices in the same system since the power supplies and device output swings employed in the older devices can easily damage the fragile oxide layers of the new thin gate oxide devices. A common approach to combining thin and thick gate oxide technologies has been to mix the different devices on a single integrated circuit or chip using special I/O buffers such that the internal and external clocks perform at different voltages. Customized manufacturing processes are expensive and are available to produce only a limited variety of devices.
One commonly employed method for fabricating gate oxides of varying thicknesses on a single chip is depicted in FIG. 1. As shown in FIG. 1A, first gate oxide layer 12 is grown on epitaxial silicon layer 10. Thereafter, first polysilicon layer 14 is blanket deposited on first gate oxide layer 12 as illustrated in FIG. 1B. Then, as further shown in FIG. 1B, patterned resist 16 is formed on first polysilicon layer 14. First polysilicon layer is then anisotropically etched using patterned resist 16 as a mask. Patterned resist 16 is stripped to provide first gate stack generally indicated at 17 in FIG. 1C. Second gate oxide layer 18 is then deposited/grown and second polysilicon layer 20 is then deposited as illustrated in FIG. 1D. Then, as illustrated in FIG. 1E, patterned resist 22 is formed on second polysilicon layer 20. Second polysilicon layer 20 and second gate oxide layer 18 are then anisotropically etched using patterned resist 22 as a mask. Thereafter, as illustrated in FIG. 1F, patterned resist 22 is stripped to provide second gate stack generally indicated at 24 having a gate oxide which is thicker than the gate oxide of first gate stack 17. It is readily apparent that multiple steps are involved in the formation of variable thickness gate oxides on a single wafer or chip.